On Rab, 2017-08-30 at 10:45 +0200, Marek Vasut wrote:
> On 08/30/2017 07:59 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-08-29 at 13:51 +0200, Marek Vasut wrote:
> > >
> > > On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > >
On 08/30/2017 07:59 AM, Chee, Tien Fong wrote:
> On Sel, 2017-08-29 at 13:51 +0200, Marek Vasut wrote:
>> On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> This config allow FPGA design loaded from FAT fs to FPGA manager.
>>>
>>> Signed-off-by: Tien Fong
On Sel, 2017-08-29 at 13:51 +0200, Marek Vasut wrote:
> On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > This config allow FPGA design loaded from FAT fs to FPGA manager.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> > configs/socfpga_arria10_defc
On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This config allow FPGA design loaded from FAT fs to FPGA manager.
>
> Signed-off-by: Tien Fong Chee
> ---
> configs/socfpga_arria10_defconfig |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> dif
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