On Thu, Oct 8, 2015 at 5:58 PM, Marek Vasut wrote:
>> mdelay(50);
>>
>> + if (is_mx6dqp()) {
>> + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST);
>
> Why don't you put this section before the mdelay(50) above ? This should
> produce the same effect as adding add
On Thursday, October 08, 2015 at 05:49:27 PM, Fabio Estevam wrote:
> PCI driver currently hangs on mx6qp.
>
> Toggle the reset bit with the appropriate timings to fix the issue.
>
> Based on the FSL kernel driver implementation.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/include/asm/arc
Hi Tim,
On Thu, Oct 8, 2015 at 2:55 PM, Tim Harvey wrote:
> Fabio,
>
> So Freescale finally connected a usable reset to the PCIe core but
> only on the QuadPlus? GPR1.29 is marked as 'reserved' in the IMX6DQRM
> and I'm unable to find a RM for the QP. Is this something that will be
> rolled into
On Thu, Oct 8, 2015 at 8:49 AM, Fabio Estevam
wrote:
> PCI driver currently hangs on mx6qp.
>
> Toggle the reset bit with the appropriate timings to fix the issue.
>
> Based on the FSL kernel driver implementation.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/include/asm/arch-mx6/iomux.h |
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