On Wed, 8 Oct 2008 21:26:34 -0700
"Liu Dave-R63238" <[EMAIL PROTECTED]> wrote:
> It is due to hardware design and logic defect, that is the
> I/O[0:7] of NAND chip is connected to LAD[7:0], so when
> the NAND chip connected to nLCS3, you have to set up the
> OR3[BCTLD] = '1' for normal operation,
It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3, you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.
Setup th
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