Re: [U-Boot] timing_cfg_2 register in FSL DDR driver

2016-07-29 Thread york sun
On 07/29/2016 08:19 AM, Thomas Schaefer wrote: > Hi York, > > with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of > timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as > (wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better

[U-Boot] timing_cfg_2 register in FSL DDR driver

2016-07-29 Thread Thomas Schaefer
Hi York, with commit 5605dc6135f6f26560ef3b0c6ebc5141c531179a you fix wr_lat bits of timing_cfg_2 register for FSL ddr driver. Unfortunately this fix is wrong as (wr_lat & 0x10) is already 5 bits. To make things clearer maybe it is better to set wr_lat this way diff --git a/drivers/ddr/fsl/ctr