Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Hector, On Thu, May 18, 2017 at 2:06 PM, Palacios, Hector wrote: > Hi Fabio, > > On Thu, 18 May 2017 17:52, Fabio Estevam wrote: >> I got very slow performance with MX6UL when U-Boot is loaded via >> serial download mode. > > That's it, actually! > I was booting the target via USB, booting fro

Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Fabio, On Thu, 18 May 2017 17:52, Fabio Estevam wrote: > I got very slow performance with MX6UL when U-Boot is loaded via > serial download mode. That's it, actually! I was booting the target via USB, booting from the NAND shows normal performance. > This gets fixed by setting the SMP bit:

Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Hector, On Thu, May 18, 2017 at 11:43 AM, Hector Palacios wrote: > In case I wasn't clear, I don't have any memory mapping problems. I have one > single > DDR chip, which internally uses two dies and two chip selects. Setting > CONFIG_NR_DRAM_BANKS to 1 (and full size) or 2 (and half size) i

Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Fabio, On 05/17/2017 11:08 PM, Fabio Estevam wrote: > Hi Hector, > > On Wed, May 17, 2017 at 5:50 AM, Palacios, Hector > wrote: > >> The code is on Github [1] (well, not the dual-die DDR3 yet) but there isn't >> much to see for this issue other than: > > I looked at your code and I see: >

Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Hector, On Wed, May 17, 2017 at 5:50 AM, Palacios, Hector wrote: > The code is on Github [1] (well, not the dual-die DDR3 yet) but there isn't > much to see for this issue other than: I looked at your code and I see: int dram_init(void) { gd->ram_size = ((ulong)CONFIG_DDR_MB * SZ_1M); ret

Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Fabio, On Wed, 17 May 2017 00:34, Fabio Estevam wrote: > Hi Hector, > > On Tue, May 16, 2017 at 1:15 PM, Palacios, Hector > wrote: >> Greetings, >> >> I'm adding support to a 1GiB DDR3 chip that internally has two dies. I > have configured the i.MX6UL memory controller for using two chip sel

Re: [U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Hi Hector, On Tue, May 16, 2017 at 1:15 PM, Palacios, Hector wrote: > Greetings, > > I'm adding support to a 1GiB DDR3 chip that internally has two dies. I have > configured the i.MX6UL memory controller for using two chip selects and > assigned 512MiB to each. Although the RAM seems to work fi

[U-Boot] Very slow mtest on i.MX6UL over dual-die DDR3 (two chip selects)

Greetings, I'm adding support to a 1GiB DDR3 chip that internally has two dies. I have configured the i.MX6UL memory controller for using two chip selects and assigned 512MiB to each. Although the RAM seems to work fine I'm experiencing extremely slow performance compared to a similar 1GiB chip