subject:"\[U\-Boot\] TLB mapping for pcie mem space for fsl corenet processors"

Re: [U-Boot] TLB mapping for pcie mem space for fsl corenet processors

2013-07-08 Thread Sughosh Ganu

hi Scott, On Tue, Jul 9, 2013 at 12:37 AM, Scott Wood wrote: > On 07/04/2013 01:13:29 PM, Sughosh Ganu wrote: > >> hi, >> The tlb entries for the pcie mem space for the corenet SoC's is done >> for 1.5GiB but certain boards use all the 4 pcie controller >> instantiations, and each controller is

Re: [U-Boot] TLB mapping for pcie mem space for fsl corenet processors

2013-07-08 Thread Scott Wood

On 07/04/2013 01:13:29 PM, Sughosh Ganu wrote: hi, The tlb entries for the pcie mem space for the corenet SoC's is done for 1.5GiB but certain boards use all the 4 pcie controller instantiations, and each controller is assigned 512MiB size in the config files. Should the tlb entries not map 2GiB

[U-Boot] TLB mapping for pcie mem space for fsl corenet processors

2013-07-04 Thread Sughosh Ganu

hi, The tlb entries for the pcie mem space for the corenet SoC's is done for 1.5GiB but certain boards use all the 4 pcie controller instantiations, and each controller is assigned 512MiB size in the config files. Should the tlb entries not map 2GiB space as against 1.5GiB. Am i missing something.