On Thursday, December 04, 2014 at 11:08:32 PM, mgerlach wrote:
> On Wed, 3 Dec 2014, Pavel Machek wrote:
> > Hi!
> >
> > > >>> altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
> > > >>> reg = <0xffd07300 0x0048>;
> > > >>> altr,pinmux-regs = <0x0 0x51010
On Wed, 3 Dec 2014, Pavel Machek wrote:
> Hi!
>
> > >>> altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
> > >>> reg = <0xffd07300 0x0048>;
> > >>> altr,pinmux-regs = <0x0 0x51010 0x51010 0x51010 0x40605
> > >>>0x40605 0x00605 0x40605
Hi!
> >>> altr,pinmux-regs = <0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
> >>> reg = <0xffd07300 0x0048>;
> >>> altr,pinmux-regs = <0x0 0x51010 0x51010 0x51010 0x40605
> >>>0x40605 0x00605 0x40605 0x40605 0x40605
> >>>0x10605 0x5
Hi,
From: s...@google.com on behalf of Simon Glass
Sent: Wednesday, December 3, 2014 9:36 AM
To: Pavel Machek
Cc: Matthew Gerlach; u-boot@lists.denx.de
Subject: Re: [U-Boot] RFC Pin Configuration Device Tree Bindings for Altera
Arria10 SOCFPGA
Hi
; Subject: Re: [U-Boot] RFC Pin Configuration Device Tree Bindings for Altera
> Arria10 SOCFPGA
>
> Hi,
>
> On 3 December 2014 at 06:48, Pavel Machek wrote:
>> Hi!
>>
>>> Altera Arria10 SOCFPGA Pin Configuration Bindings
>>>
>>> This document
+CC: Matthew Gerlach
Not sure why the original submitter was left on this response.
On 12/3/14, 11:36 AM, Simon Glass wrote:
> Hi,
>
> On 3 December 2014 at 06:48, Pavel Machek wrote:
>> Hi!
>>
>>> Altera Arria10 SOCFPGA Pin Configuration Bindings
>>>
>>> This document describes device tree bin
Hi,
On 3 December 2014 at 06:48, Pavel Machek wrote:
> Hi!
>
>> Altera Arria10 SOCFPGA Pin Configuration Bindings
>>
>> This document describes device tree bindings required to perform
>> configuration
>> of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to
>> be compact and
Hi!
> Altera Arria10 SOCFPGA Pin Configuration Bindings
>
> This document describes device tree bindings required to perform configuration
> of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to
> be compact and easy to be consumed only by a SPL running in a small on-chip
> ra
Altera Arria10 SOCFPGA Pin Configuration Bindings
This document describes device tree bindings required to perform configuration
of the pins for an Altera Arria10 SOCFPGA . The bindings are intended to
be compact and easy to be consumed only by a SPL running in a small on-chip
ram before external
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