Hi Dave,
It still shows data tlb error tho.
I found it occur error around the GET_GOT of start.s.
The SRR0 and SRR1 show the error address of system.map is _start_cont.
Suspect the DDR setting problem ?? But I thought all the DDR setting are
from SPD.
So, I didn't set any entry of D
> >EELADR - 0XF401, it is INIT_RAM address, why the
> transaction with
> >address(0xF401) go to system bus?
> >It should keep in the cache due to cache lock, never out to
> system bus.
>
> I don't know why... and it just happened shall I allocate
> a entry of tlb for it?? or cover
>EELADR - 0XF401, it is INIT_RAM address, why the transaction
>with address(0xF401) go to system bus?
>It should keep in the cache due to cache lock, never out to system bus.
I don't know why... and it just happened shall I allocate a entry of tlb
for it?? or cover it in some
space ?
> My board can't boot normally, and I found it just hang in
> data tlb error
> through the system.map.
> Could any one help for this?
> Some regisers are as below:
>
> DEAR: 0xf400fff0 (L1 init ram base address is 0xf401)
> IVPR : 0xfff8 , IVPR3
Hi all,
My board can't boot normally, and I found it just hang in data tlb error
through the system.map.
Could any one help for this?
Some regisers are as below:
DEAR: 0xf400fff0 (L1 init ram base address is 0xf401)
IVPR : 0xfff8 , IVPR3: 0x
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