On 04/04/2014 11:25 AM, Stefano Babic wrote:
Hi Helmut,
On 04/04/2014 01:13, Simon Glass wrote:
1) add option to 'go' command, which is hard as it has variable arguments
2) add another go command
3) use an environment variable to set the option for 'go'
Theoretically I could use a u-boot imag
Hi Helmut,
On 04/04/2014 01:13, Simon Glass wrote:
>> 1) add option to 'go' command, which is hard as it has variable arguments
>> 2) add another go command
>> 3) use an environment variable to set the option for 'go'
>>
>> Theoretically I could use a u-boot image to encapsulate the second u-boot
Hi Hemut,
On 31 March 2014 05:29, Helmut Raiger wrote:
> On 02/13/2014 10:03 AM, Helmut Raiger wrote:
>
>>
>>
>> But you just inspired me! There are probably interrupts running
>> for some time when the second u-boot starts and the relocation
>> might destroy part of the interrupt entry points .
On 02/13/2014 10:03 AM, Helmut Raiger wrote:
But you just inspired me! There are probably interrupts running
for some time when the second u-boot starts and the relocation
might destroy part of the interrupt entry points
Thx for asking the right questions.
I'll have to check this.
Helmut
On 02/12/2014 10:59 PM, Scott Wood wrote:
Most operations are read (we use a separate YAFFS partition for time
predictable writes),
so UBI will relocate read-only blocks anyway (due to read disturbances),
I think the
effect wont be too dramatic, but don't make me proof that ;-)
This sounds like
On 02/12/2014 11:45 AM, Andreas Bießmann wrote:
Hi Helmut,
On 02/12/2014 10:56 AM, Helmut Raiger wrote:
I understand the first two points, but why do you store the kernel again
with 1bit HW-ECC ? The second U-Boot is able to check with 4bit BCH and
your NAND requires 4bit.
This is mainly due t
On Mon, 2014-02-10 at 13:57 +0100, Helmut Raiger wrote:
> On 02/10/2014 01:14 PM, Andreas Bießmann wrote:
> > - we have a hardware design bug
> > - we have a few hundred i.MX31 TT-01 devices in the field
> > - the i.MX31 rom boot loader is only capable of using 1bit HW-ECC
> > (loading the first pa
Hi Helmut,
On 02/12/2014 10:56 AM, Helmut Raiger wrote:
>> I understand the first two points, but why do you store the kernel again
>> with 1bit HW-ECC ? The second U-Boot is able to check with 4bit BCH and
>> your NAND requires 4bit.
>
> This is mainly due to performance requirements. Using 4bit
Hi Helmut,
On 12/02/2014 10:56, Helmut Raiger wrote:
> This is mainly due to performance requirements. Using 4bit BCH
> increases overhead and makes DMA (currently not used in the
> kernel driver) a lot slower. We thought we might slip through with
> 1bit HW-ECC, but we will test this (hopefully n
Hi Stefano,
Hi Helmut,
I understand the first two points, but why do you store the kernel again
with 1bit HW-ECC ? The second U-Boot is able to check with 4bit BCH and
your NAND requires 4bit.
This is mainly due to performance requirements. Using 4bit BCH
increases overhead and makes DMA (cur
Hi Helmut,
On 10/02/2014 12:11, Helmut Raiger wrote:
>
> So the idea was:
>
> - use a small u-boot (<128kB) in the first PEB of the NAND (written with
> 1bit HW-ECC) that supports 4bit BCH
> - let it load a second u-boot (<512kB) from the next 4 PEBs (written
> with 4bit BCH)
> - jump to the se
On 02/10/2014 01:14 PM, Andreas Bießmann wrote:
- we have a hardware design bug
- we have a few hundred i.MX31 TT-01 devices in the field
- the i.MX31 rom boot loader is only capable of using 1bit HW-ECC
(loading the first page (2k) from the NAND)
- the NAND chip specifies a requirement of 1bit E
Dear Helmut Raiger,
On 02/10/2014 12:11 PM, Helmut Raiger wrote:
> Hi,
>
> to give you some background why we would want to do something
> (strange) like this:
>
> - we have a hardware design bug
> - we have a few hundred i.MX31 TT-01 devices in the field
> - the i.MX31 rom boot loader is on
Hi,
to give you some background why we would want to do something
(strange) like this:
- we have a hardware design bug
- we have a few hundred i.MX31 TT-01 devices in the field
- the i.MX31 rom boot loader is only capable of using 1bit HW-ECC
(loading the first page (2k) from the NAND)
-
14 matches
Mail list logo
