Alessandro Rubini wrote:
>> Does someone have the s3c2410 manual?
>
> 2410UserManual.pdf:
>
>USER'S MANUAL
>S3C2410A 200MHz & 266MHz 32-Bit RISC Microprocessor Revision 1.0
>
>[...]
>
>INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each
>of which is rela
> Does someone have the s3c2410 manual?
2410UserManual.pdf:
USER'S MANUAL
S3C2410A 200MHz & 266MHz 32-Bit RISC Microprocessor Revision 1.0
[...]
INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each
of which is related to an interrupt source. [...]
Bits 0..10
Wolfgang Denk wrote:
> Dear Tom,
>
> In message <902963.84935...@web15002.mail.cnb.yahoo.com>
> =?utf-8?B?6Zu3IOmrmA==?= wrote:
>> In u-boot-2009.08/cpu/arm920t/start.S, the instruction of line 158 is
>> "ldr r1, x3ff", but the effective bits in INTSUBMSK register of
>> S3C2410 are [10...0]. So I
Dear Tom,
In message <902963.84935...@web15002.mail.cnb.yahoo.com>
=?utf-8?B?6Zu3IOmrmA==?= wrote:
>
> In u-boot-2009.08/cpu/arm920t/start.S, the instruction of line 158 is
> "ldr r1, x3ff", but the effective bits in INTSUBMSK register of
> S3C2410 are [10...0]. So I think "0x3ff" is not right.
In u-boot-2009.08/cpu/arm920t/start.S, the instruction of line 158 is "ldr
r1, =0x3ff", but the effective bits in INTSUBMSK register of S3C2410 are
[10...0]. So I think "0x3ff" is not right. The right value should be "0x7ff".
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