Re: [U-Boot] [u-boot] AR8033 SerDes Test and System Mode Control setting issue

> -Original Message- > From: Sekhar Nori [mailto:nsek...@ti.com] > Sent: Tuesday, January 17, 2017 3:23 AM > To: Ken.Lin; joe.hershber...@ni.com > Cc: Peter.Stretz; mugunthan...@ti.com; Peter.Chiang; Chiming.Lee; u- > b...@lists.denx.de; albert.u.ub...@aribaud.net; w...@denx.de > Subject:

Re: [U-Boot] [u-boot] AR8033 SerDes Test and System Mode Control setting issue

Hi Ken Lin, On Tuesday 17 January 2017 03:44 AM, Ken.Lin wrote: > Hi Joe and Mugunthan, > > We encountered the voltage peak issue while doing the IEEE PHY conformance > test, which has to do with the AR8033 register (SetDes Test and System Mode > Control) setting in u-boot. > In your commit cha

[U-Boot] [u-boot] AR8033 SerDes Test and System Mode Control setting issue

Hi Joe and Mugunthan, We encountered the voltage peak issue while doing the IEEE PHY conformance test, which has to do with the AR8033 register (SetDes Test and System Mode Control) setting in u-boot. In your commit change info, you tried to enable tx clock delay by setting bit 8 to 1 (filling