Hi,
On 20.7.2018 18:17, Luis Araneda wrote:
> Hi Michal,
>
> On Fri, Jul 20, 2018 at 6:38 AM Michal Simek wrote:
>> On 20.7.2018 01:37, Luis Araneda wrote:
>>> Hi Michal,
>>>
>>> On Thu, Jul 19, 2018 at 2:23 AM Michal Simek
>>> wrote:
>> We need that functionality first but then enable it for
Hi Michal,
On Fri, Jul 20, 2018 at 6:38 AM Michal Simek wrote:
> On 20.7.2018 01:37, Luis Araneda wrote:
> > Hi Michal,
> >
> > On Thu, Jul 19, 2018 at 2:23 AM Michal Simek
> > wrote:
> We need that functionality first but then enable it for all boards is
> fine for me and via one patch.
Ok
>
Hi,
On 20.7.2018 01:37, Luis Araneda wrote:
> Hi Michal,
>
> On Thu, Jul 19, 2018 at 2:23 AM Michal Simek wrote:
>> On 18.7.2018 20:02, Luis Araneda wrote:
>>> [...]
>>> I didn't send them because just changing the defconfig isn't enough,
>>
>> It should be enough. It is configuration option and
Hi Michal,
On Thu, Jul 19, 2018 at 2:23 AM Michal Simek wrote:
> On 18.7.2018 20:02, Luis Araneda wrote:
> > [...]
> > I didn't send them because just changing the defconfig isn't enough,
>
> It should be enough. It is configuration option and just enabling that
> feature. You should still be abl
On 18.7.2018 20:02, Luis Araneda wrote:
> Hi Michal,
>
> On Wed, Jul 18, 2018 at 4:00 AM Michal Simek wrote:
>> Can you please also send defconfig/config changes?
>> Separate patch is fine.
>
> The changes required to the defconfigs test/support this are:
> CONFIG_SPL_LOAD_FIT=y
> CONFIG_SPL_FPG
Hi Michal,
On Wed, Jul 18, 2018 at 4:00 AM Michal Simek wrote:
> Can you please also send defconfig/config changes?
> Separate patch is fine.
The changes required to the defconfigs test/support this are:
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FPGA_SUPPORT=y
I didn't send them because just changing th
On 18.7.2018 09:41, Luis Araneda wrote:
> This series implements FPGA bitstream loading from SPL.
> Programming the FPGA from the SPL is necessary on some boards,
> like the Zybo, because the FPGA fabric routes the I2C bus to an
> EEPROM for reading the Ethernet MAC address.
>
> The bitstream is l
This series implements FPGA bitstream loading from SPL.
Programming the FPGA from the SPL is necessary on some boards,
like the Zybo, because the FPGA fabric routes the I2C bus to an
EEPROM for reading the Ethernet MAC address.
The bitstream is loaded from a FIT image into a dynamically-allocated
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