Hi Sughosh,
On Wed, 10 Jul 2013 23:04:45 +0530, Sughosh Ganu
wrote:
> hi Albert,
>
> On Wed Jul 10, 2013 at 02:30:30PM +0200, Albert ARIBAUD wrote:
>
> > > > You are correct re the other policies of the DDI0198E (ARM926EJ-S
> > > > TRM) MMU -- page 3-11, bits 3-2 of the section descriptor. Not
hi Albert,
On Wed Jul 10, 2013 at 02:30:30PM +0200, Albert ARIBAUD wrote:
> > > You are correct re the other policies of the DDI0198E (ARM926EJ-S
> > > TRM) MMU -- page 3-11, bits 3-2 of the section descriptor. Note however
> > > that you may have to refer to your specific SoC's TRM or equivalent
Hi Sughosh,
On Wed, 10 Jul 2013 15:35:10 +0530, Sughosh Ganu
wrote:
> hi Albert,
>
> On Tue Jul 09, 2013 at 10:28:13AM +0200, Albert ARIBAUD wrote:
>
> > > > The arm926ej-s data cache does not have a single fixed policy, and
> > > > does not have a bypass-on-write policy, only write-through an
hi Albert,
On Tue Jul 09, 2013 at 10:28:13AM +0200, Albert ARIBAUD wrote:
> > > The arm926ej-s data cache does not have a single fixed policy, and
> > > does not have a bypass-on-write policy, only write-through and
> > > copy-back.
> > >
> > > Other, more complex, policies may be defined, but a
Hi Sughosh,
On Tue, 9 Jul 2013 11:41:34 +0530, Sughosh Ganu
wrote:
> hi Albert,
>
> On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
>
>
>
> > > > Invalidating the cache in addition to flushing it would not prevent
> > > > further writes from dirtying the cache lines if they ha
hi Albert,
On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
> > > Invalidating the cache in addition to flushing it would not prevent
> > > further writes from dirtying the cache lines if they happen before
> > > the cache is disabled.
> >
> > I have a doubt on this. The arm926ej
hi Albert,
On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote:
> > > Invalidating the cache in addition to flushing it would not prevent
> > > further writes from dirtying the cache lines if they happen before
> > > the cache is disabled.
> >
> > I have a doubt on this. The arm926ej
Hi Sughosh,
On Mon, 8 Jul 2013 19:37:22 +0530, Sughosh Ganu
wrote:
> hi Albert,
>
> On Mon Jul 08, 2013 at 02:32:16PM +0200, Albert ARIBAUD wrote:
> > Hi Sughosh,
> >
> > On Mon, 8 Jul 2013 17:38:46 +0530, Sughosh Ganu
> > wrote:
> >
> > > hi Albert,
> > > On Mon Jul 08, 2013 at 12:22:57PM +
hi Albert,
On Mon Jul 08, 2013 at 02:32:16PM +0200, Albert ARIBAUD wrote:
> Hi Sughosh,
>
> On Mon, 8 Jul 2013 17:38:46 +0530, Sughosh Ganu
> wrote:
>
> > hi Albert,
> > On Mon Jul 08, 2013 at 12:22:57PM +0200, Albert ARIBAUD wrote:
> >
> >
> >
> > > It you flush first then disable, you leav
Hi Sughosh,
On Mon, 8 Jul 2013 17:38:46 +0530, Sughosh Ganu
wrote:
> hi Albert,
> On Mon Jul 08, 2013 at 12:22:57PM +0200, Albert ARIBAUD wrote:
>
>
>
> > It you flush first then disable, you leave a time window between the
> > two where a write to the cache can happen (either because your co
hi Albert,
On Mon Jul 08, 2013 at 12:22:57PM +0200, Albert ARIBAUD wrote:
> It you flush first then disable, you leave a time window between the
> two where a write to the cache can happen (either because your code
> does one, or because the compiler optimized one in). If it happens,
> then you
hi Albert,
On Mon Jul 08, 2013 at 12:22:57PM +0200, Albert ARIBAUD wrote:
> It you flush first then disable, you leave a time window between the
> two where a write to the cache can happen (either because your code
> does one, or because the compiler optimized one in). If it happens,
> then you
Hi Bo,
On Mon, 08 Jul 2013 07:33:18 +0800, Bo Shen
wrote:
> Hi Albert,
>
> 于 7/6/2013 5:02 AM, Albert ARIBAUD 写道:
> > Hi Bo,
> >
> > On Tue, 2 Jul 2013 12:35:54 +, Bo Shen
> > wrote:
> >
> >> flush cache before disable it
> >>
> >> Signed-off-by: Bo Shen
> >> ---
> >> arch/arm/cpu/arm9
Hi Albert,
于 7/6/2013 5:02 AM, Albert ARIBAUD 写道:
Hi Bo,
On Tue, 2 Jul 2013 12:35:54 +, Bo Shen
wrote:
flush cache before disable it
Signed-off-by: Bo Shen
---
arch/arm/cpu/arm926ejs/cpu.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm9
Hi Bo,
On Tue, 2 Jul 2013 12:35:54 +, Bo Shen
wrote:
> flush cache before disable it
>
> Signed-off-by: Bo Shen
> ---
> arch/arm/cpu/arm926ejs/cpu.c |5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu
flush cache before disable it
Signed-off-by: Bo Shen
---
arch/arm/cpu/arm926ejs/cpu.c |5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c
index 626384c..10aa165 100644
--- a/arch/arm/cpu/arm926ejs/cpu.c
+++ b/arc
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