On Sun, Apr 30, 2017 at 2:57 PM, Daniel Schwierzeck
wrote:
> From: Paul Burton
>
> On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
> present. When there is no IOCU we need to writeback or invalidate the
> data caches at appropriate points. Perform this cache maintenance i
On 30 April 2017 at 13:57, Daniel Schwierzeck
wrote:
> From: Paul Burton
>
> On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
> present. When there is no IOCU we need to writeback or invalidate the
> data caches at appropriate points. Perform this cache maintenance in
> th
From: Paul Burton
On MIPS systems DMA isn't coherent with the CPU caches unless an IOCU is
present. When there is no IOCU we need to writeback or invalidate the
data caches at appropriate points. Perform this cache maintenance in
the pch_gbe driver which is used on the MIPS Boston development boa
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