Refer to "Table 5-1. LS1 memory map" in "LS1 SoC Architecture Specification".
It shows that:
Start Address: 0x2 Size: 16MB DCSR
Or, see the dcsr node in arch/arm/boot/dts/ls1021a.dtsi in Linux.
Thanks,
Chenhui
From: York Sun
Sent: Tuesday, De
On 12/06/2014 06:46 AM, Alison Wang wrote:
> This patch adds NAND boot support for LS1021AQDS board. SPL
> framework is used. PBL initialize the internal RAM and copy
> SPL to it, then SPL initialize DDR using SPD and copy u-boot
> from NAND flash to DDR, finally SPL transfer control to u-boot.
>
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ali
On 12/02/2014 11:00 PM, Alison Wang wrote:
> This patch adds NAND boot support for LS1021AQDS board. SPL
> framework is used. PBL initialize the internal RAM and copy
> SPL to it, then SPL initialize DDR using SPD and copy u-boot
> from NAND flash to DDR, finally SPL transfer control to u-boot.
>
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ali
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