> According to the 8548 and 8572 manuals (not sure about others...), the
> TBIPA register value for all PHYs is 0x0 at reset, which is reserved
> according to the manuals. The description of the MIIMADD register
> supports this by stating: "Up to 31 PHYs can be addressed (0 is
> reserved)". So I
Hi Andy,
> >> > @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
> >> > {
> >> >struct tsec_private *priv = (struct tsec_private *)dev->priv;
> >> >struct phy_info *curphy;
> >> > - volatile tsec_t *phyregs = priv->phyregs;
> >> >volatile tsec_t *reg
On Mon, Sep 15, 2008 at 5:17 PM, Peter Tyser <[EMAIL PROTECTED]> wrote:
> On Mon, 2008-09-15 at 16:13 -0500, Andy Fleming wrote:
>> > @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
>> > {
>> >struct tsec_private *priv = (struct tsec_private *)dev->priv;
>> >struc
On Mon, 2008-09-15 at 16:13 -0500, Andy Fleming wrote:
> > @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
> > {
> >struct tsec_private *priv = (struct tsec_private *)dev->priv;
> >struct phy_info *curphy;
> > - volatile tsec_t *phyregs = priv->phyregs;
> >
> @@ -299,12 +301,10 @@ static int init_phy(struct eth_device *dev)
> {
>struct tsec_private *priv = (struct tsec_private *)dev->priv;
>struct phy_info *curphy;
> - volatile tsec_t *phyregs = priv->phyregs;
>volatile tsec_t *regs = priv->regs;
>
>/* Assign a P
Andy,
You're much more qualified than me to accept or reject this, so if you
don't mind, please pick it up.
regards,
Ben
Peter Tyser wrote:
> Fix TBI PHY accesses to use the proper offset in CPU register space. The
> previous code would incorrectly access the TBI PHY by reading/writing to CPU
Fix TBI PHY accesses to use the proper offset in CPU register space. The
previous code would incorrectly access the TBI PHY by reading/writing to CPU
register space at the same location as would be used to access external PHYs.
Signed-off-by: Peter Tyser <[EMAIL PROTECTED]>
---
Dohh... v2 of the
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