On 16 December 2014 at 02:33, Bin Meng wrote:
> On Tue, Dec 16, 2014 at 1:02 PM, Simon Glass wrote:
>> Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
>> means of starting up the CPU. One result is that microcode updates can only
>> be done before RAM is available and theref
On Tue, Dec 16, 2014 at 1:02 PM, Simon Glass wrote:
> Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
> means of starting up the CPU. One result is that microcode updates can only
> be done before RAM is available and therefore parsing of the device tree
> is impracticle.
>
>
Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
means of starting up the CPU. One result is that microcode updates can only
be done before RAM is available and therefore parsing of the device tree
is impracticle.
Worse, the addess of the microcode update must be stored in ROM
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