On 10/09/16 17:55, Daniel Schwierzeck wrote:
> Am 09.09.2016 um 15:44 schrieb Paul Burton:
>> This patch adds support for initialising & maintaining L2 caches on MIPS
>> systems. The L2 cache configuration may be advertised through either
>> coprocessor 0 or the MIPS Coherence Manager depending upo
Am 09.09.2016 um 15:44 schrieb Paul Burton:
> This patch adds support for initialising & maintaining L2 caches on MIPS
> systems. The L2 cache configuration may be advertised through either
> coprocessor 0 or the MIPS Coherence Manager depending upon the system,
> and support for both is included
This patch adds support for initialising & maintaining L2 caches on MIPS
systems. The L2 cache configuration may be advertised through either
coprocessor 0 or the MIPS Coherence Manager depending upon the system,
and support for both is included.
If the L2 can be bypassed then we bypass it early i
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