On 05/18/2018 04:05 PM, Ley Foon Tan wrote:
> Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
> accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
> conditional build in order this file can by shared across other SOCFPGAs.
>
> Signed-off-by: Chin Liang
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.
Signed-off-by: Chin Liang See
Signed-off-by: Ley Foon Tan
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arch/arm/mach-
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