Re: [U-Boot] [PATCH v2] x86: baytrail: pci region 3 is not always mapped to end of ram

2015-06-03 Thread Andrew Bradford
On 06/03 12:18, and...@bradfordembedded.com wrote: > From: Andrew Bradford > > Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF > and additional SDRAM is mapped from 0x1 and up. There is a > physical memory hole from 0x8000 to 0x for other uses. > Becau

[U-Boot] [PATCH v2] x86: baytrail: pci region 3 is not always mapped to end of ram

2015-06-03 Thread andrew
From: Andrew Bradford Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF and additional SDRAM is mapped from 0x1 and up. There is a physical memory hole from 0x8000 to 0x for other uses. Because of this, PCI region 3 should only try to use up to the amoun