On 24 April 2015 at 17:04, D. Dueck wrote:
> As requested:
> Tested-by: David Dueck
>
>
> Am Freitag, 24. April 2015 schrieb Jagan Teki :
>>
>> On 7 April 2015 at 05:55, Tom Rini wrote:
>> > On Wed, Apr 01, 2015 at 04:21:50PM +0100, Andy Pont wrote:
>> >> Hi David,
>> >>
>> >>
>> >>
>> >> >
On 7 April 2015 at 05:55, Tom Rini wrote:
> On Wed, Apr 01, 2015 at 04:21:50PM +0100, Andy Pont wrote:
>> Hi David,
>>
>>
>>
>> > for (i = 0; i < len; i++) {
>> > /* wait till TX register is empty (TXS == 1) */
>> > + start = get_timer(0);
>> > while (!(readl
As requested:
Tested-by: David Dueck
Am Freitag, 24. April 2015 schrieb Jagan Teki :
> On 7 April 2015 at 05:55, Tom Rini >
> wrote:
> > On Wed, Apr 01, 2015 at 04:21:50PM +0100, Andy Pont wrote:
> >> Hi David,
> >>
> >>
> >>
> >> > for (i = 0; i < len; i++) {
> >> > /* wait til
On Wed, Apr 01, 2015 at 04:21:50PM +0100, Andy Pont wrote:
> Hi David,
>
>
>
> > for (i = 0; i < len; i++) {
> > /* wait till TX register is empty (TXS == 1) */
> > + start = get_timer(0);
> > while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
> >
Hi David,
> for (i = 0; i < len; i++) {
> /* wait till TX register is empty (TXS == 1) */
> + start = get_timer(0);
> while (!(readl(&ds->regs->channel[ds->slave.cs].chstat) &
>OMAP3_MCSPI_CHSTAT_TXS)) {
> -
On 1 April 2015 at 17:50, David Dueck wrote:
> The timeout value is never reset during the transfer. This means that when
> transferring more data we eventually trigger the timeout.
>
> This was reported on the mailing list:
> "Spansion SPI flash read timeout with AM335x"
>
> Signed-off-by: David
The timeout value is never reset during the transfer. This means that when
transferring more data we eventually trigger the timeout.
This was reported on the mailing list:
"Spansion SPI flash read timeout with AM335x"
Signed-off-by: David Dueck
CC: Tom Rini
CC: Jagannadh Teki
CC: Stefan Roese
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