subject:"\[U\-Boot\] \[PATCH v2\] rockchip\: rk3288\: Fix pinctrl for GPIO bank 0"

Re: [U-Boot] [PATCH v2] rockchip: rk3288: Fix pinctrl for GPIO bank 0

2016-07-27 Thread Simon Glass

On 25 July 2016 at 03:16, Kever Yang wrote: > Hi John, > > > On 07/25/2016 05:02 PM, John Keeping wrote: >> >> Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers >> rather than the GRF registers. In the GRF the top half of the register >> is used as a mask so that some bits ca

Re: [U-Boot] [PATCH v2] rockchip: rk3288: Fix pinctrl for GPIO bank 0

2016-07-25 Thread Kever Yang

Hi John, On 07/25/2016 05:02 PM, John Keeping wrote: Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this

[U-Boot] [PATCH v2] rockchip: rk3288: Fix pinctrl for GPIO bank 0

2016-07-25 Thread John Keeping

Bank 0 is the "PMU GPIO" bank which is controlled by the PMU registers rather than the GRF registers. In the GRF the top half of the register is used as a mask so that some bits can be updated without affecting the others, but in the PMU this feature is not provided and the top half of the registe