-Original Message-
From: Bin Meng [mailto:bmeng...@gmail.com]
Sent: Monday, October 05, 2009 1:59 PM
To: Dudhat Dipen-B09055
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Driver
Hi Dipen,
On Thu, Oct 1, 2009 at 12:48 PM, Dudhat
Hi Dipen,
On Thu, Oct 1, 2009 at 12:48 PM, Dudhat Dipen-B09055
wrote:
>
> Hi Bin,
>
> We can know the block transfer complete using IRQSTAT(Transfer
> Complete).
> But reading & writing in PIO mode takes time for byte by byte transfers
> and there is no way to poll that transfer, that's why I hav
transfer complete *\
Is that ok ??
Regards,
Dipen
-Original Message-
From: Bin Meng [mailto:bmeng...@gmail.com]
Sent: Monday, September 28, 2009 4:41 AM
To: Dudhat Dipen-B09055
Cc: u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Drive
On Thu, Sep 10, 2009 at 9:37 PM, Dipen Dudhat
wrote:
> + while (size && (!(irqstat & IRQSTAT_TC))) {
> + udelay(100);
> + irqstat = in_be32(®s->irqstat);
> + databuf = in_le32(®s->datpor
-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC
Controller Driver
Dear Dipen Dudhat,
In message <1252589856-4970-1-git-send-email-dipen.dud...@freescale.com>
you wrote:
> On some Freescale SoC Internal DMA of eSDHC controller has bug.
>
> So PIO Mode has introduced to do data
Dear Dipen Dudhat,
In message <1252904203-9129-1-git-send-email-dipen.dud...@freescale.com> you
wrote:
> On some Freescale SoC Internal DMA of eSDHC controller has bug.
>
> So PIO Mode has introduced to do data transfer using CPU.
> In PIO mode data transfer performance will be degraded by a lar
Dear Dipen Dudhat,
In message <1252589856-4970-1-git-send-email-dipen.dud...@freescale.com> you
wrote:
> On some Freescale SoC Internal DMA of eSDHC controller has bug.
>
> So PIO Mode has introduced to do data transfer using CPU.
> In PIO mode data transfer performance will be degraded by a lar
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large extent.
Note:
In PIO mode multiple block read/write requires delay to complete the transfer.
Signed-off-by:
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large extent.
Note:
In PIO mode multiple block read/write requires delay to complete the transfer.
Signed-off-by:
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