On Wed, Feb 4, 2015 at 3:38 PM, FengHua wrote:
>> config TARGET_LS2085A_SIMU
>> bool "Support ls2085a_simu"
>> select ARM64
>> + select ARMV8_MULTIENTRY
>>
> VEXPRESS_AEMV8A and VEXPRESS_AEMV8A_SEMI are
> defaultly single entry?
Yes.
> That means we always has ATF exist.
Not n
hi Linus,
The following is some advice about the multi entry patch.
> While the Freescale ARMv8 board LS2085A will enter U-Boot both
> on a master and a secondary (slave) CPU, this is not the common
> behaviour on ARMv8 platforms. The norm is that U-Boot is entered
> from the master
On Fri, Jan 30, 2015 at 3:27 PM, FengHua wrote:
>> While the Freescale ARMv8 board LS2085A will enter U-Boot both
>> on a master and a secondary (slave) CPU, this is not the common
>> behaviour on ARMv8 platforms. The norm is that U-Boot is entered
>> from the master CPU only, while the other CPU
hi Linus:
> While the Freescale ARMv8 board LS2085A will enter U-Boot both
> on a master and a secondary (slave) CPU, this is not the common
> behaviour on ARMv8 platforms. The norm is that U-Boot is entered
> from the master CPU only, while the other CPUs are kept in
> WFI (wait for interru
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code determ
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