On Fri 2015-12-18 08:48:39, 圣江 吴 wrote:
>
>
> On Dec 18, 2015, at 12:47 AM, Chin Liang See wrote:
>
> Hi Shangjiang
>
> On Fri, 2015-12-18 at 16:43 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
>
> Signed-off-by: shengjiangwu
> Cc: Chin Lia
On Dec 18, 2015, at 12:47 AM, Chin Liang See wrote:
Hi Shangjiang
On Fri, 2015-12-18 at 16:43 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.
Signed-off-by: shengjiangwu
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc:
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.
Signed-off-by: shengjiangwu
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Stefan Roese
---
Changes for v2:
- fixed wrong perpll for QSPI
---
board/altera/cyclone5-socdk/qts/pll_c
Hi Shangjiang
On Fri, 2015-12-18 at 16:43 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[15-20] for QSPI.
> Updated QSPI clock.
>
> Signed-off-by: shengjiangwu
> Cc: Chin Liang See
> Cc: Dinh Nguyen
> Cc: Dinh Nguyen
> Cc: Pavel Machek
> Cc: Marek Vasut
> Cc: Stefan Roese
> ---
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