Re: [U-Boot] [PATCH V2 1/4] EXYNOS5: Change parent clock of FIMD to MPLL

On 2012년 12월 15일 14:13, Minkyu Kang wrote: Dear Donghwa, On 13/12/12 20:29, Ajay Kumar wrote: With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar Acked-by: Simon Glass

Re: [U-Boot] [PATCH V2 1/4] EXYNOS5: Change parent clock of FIMD to MPLL

Dear Donghwa, On 13/12/12 20:29, Ajay Kumar wrote: > With VPLL as source clock to FIMD, > Exynos DP Initializaton was failing sometimes with unstable clock. > Changing FIMD source to MPLL resolves this issue. > > Signed-off-by: Ajay Kumar > Acked-by: Simon Glass > --- > arch/arm/cpu/armv7/exyn

[U-Boot] [PATCH V2 1/4] EXYNOS5: Change parent clock of FIMD to MPLL

With VPLL as source clock to FIMD, Exynos DP Initializaton was failing sometimes with unstable clock. Changing FIMD source to MPLL resolves this issue. Signed-off-by: Ajay Kumar Acked-by: Simon Glass --- arch/arm/cpu/armv7/exynos/clock.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(