On Mon, Dec 4, 2017 at 2:31 AM, Peng Fan wrote:
> + switch (frac_pll) {
> + case ARM_PLL_CLK:
> + pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
> + pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
> + pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
> +
Add clock driver to support i.MX8M.
There are two kind PLLs, FRAC pll and SSCG pll. ROM already
configured SYS PLL1/2, we only need to configure the output.
ocotp/i2c/pll decoding and configuration/usdhc/lcdif/dram pll/
enet clock are configured in the code.
Signed-off-by: Peng Fan
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arch/arm
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