Hi Rajesh,
Sorry for the delay, patch looks good.
On Feb 5, 2014, at 7:18 AM, Rajeshwari Shinde wrote:
> From: Rajeshwari S Shinde
>
> This patch corrects the divider value written to CLKDIV register.
> Since SDCLKIN is divided inside controller by the DIVRATIO value set
> in the CLKSEL regist
Hi Pantelis Antoniou,
Please do let me know if any coments on the same.
Regards,
Rajeshwari
On Thu, Feb 6, 2014 at 7:24 AM, Jaehoon Chung wrote:
> Hi.
>
> Right, It's reasonable. Looks good to me.
>
> Acked-by: Jaehoon Chung
>
> Best Regards,
> Jaehoon Chung
>
> On 02/05/2014 02:58 PM, Rajeshw
Hi.
Right, It's reasonable. Looks good to me.
Acked-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
On 02/05/2014 02:58 PM, Rajeshwari Birje wrote:
> Hi All,
>
> CCing Jaehoon Chung.
>
> Regards,
> Rajeshwari
>
> On Wed, Feb 5, 2014 at 10:48 AM, Rajeshwari Shinde
> wrote:
>> From: Rajeshwar
Hi All,
CCing Jaehoon Chung.
Regards,
Rajeshwari
On Wed, Feb 5, 2014 at 10:48 AM, Rajeshwari Shinde
wrote:
> From: Rajeshwari S Shinde
>
> This patch corrects the divider value written to CLKDIV register.
> Since SDCLKIN is divided inside controller by the DIVRATIO value set
> in the CLKSEL re
From: Rajeshwari S Shinde
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN
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