Re: [U-Boot] [PATCH REPOST2] spi: tegra: clear RDY bit prior to every transfer

On Tue, Dec 17, 2013 at 4:17 AM, Stephen Warren wrote: > From: Yen Lin > > The RDY bit indicates that a transfer is complete. This needs to be > cleared by SW before every single HW transaction, rather than only > at the start of each SW transaction (those being made up of n HW > transactions). >

[U-Boot] [PATCH REPOST2] spi: tegra: clear RDY bit prior to every transfer

From: Yen Lin The RDY bit indicates that a transfer is complete. This needs to be cleared by SW before every single HW transaction, rather than only at the start of each SW transaction (those being made up of n HW transactions). It seems that earlier HW may have cleared this bit autonomously whe