Re: [U-Boot] [PATCH 8/8] net: zynq: Fix MDC setting for zynq

2015-11-04 Thread Joe Hershberger
On Wed, Nov 4, 2015 at 7:40 AM, Michal Simek wrote: > On 11/02/2015 10:39 PM, Joe Hershberger wrote: >> On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek >> wrote: >>> Based on spec: >>> "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and >>> write operations)" >>> Zynq is running

Re: [U-Boot] [PATCH 8/8] net: zynq: Fix MDC setting for zynq

2015-11-04 Thread Michal Simek
On 11/02/2015 10:39 PM, Joe Hershberger wrote: > On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek > wrote: >> Based on spec: >> "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and >> write operations)" >> Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 > > I

Re: [U-Boot] [PATCH 8/8] net: zynq: Fix MDC setting for zynq

2015-11-02 Thread Joe Hershberger
On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek wrote: > Based on spec: > "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and > write operations)" > Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 Isn't it dependent on which board and what the clock setup is

[U-Boot] [PATCH 8/8] net: zynq: Fix MDC setting for zynq

2015-10-27 Thread Michal Simek
Based on spec: "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations)" Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47 which is above of 2.5MHz. Using 48 divider will give us correct setting according spec (111/48=2.31). Signed-off-by: Michal