Hi, Stefano
On Wed, Jun 10, 2015 at 11:40:38AM +0200, Stefano Babic wrote:
>Hi Peng,
>
>On 10/06/2015 10:06, Peng Fan wrote:
>> 1. Add DDR script for mx6qpsabreauto board.
>> 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
>>and init the enet pll output to 125Mhz.
>
Hi Peng,
On 10/06/2015 10:06, Peng Fan wrote:
> 1. Add DDR script for mx6qpsabreauto board.
> 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
>and init the enet pll output to 125Mhz.
> 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
>
> Build target: mx6qpsabrea
1. Add DDR script for mx6qpsabreauto board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
U-Boot 2015.07-rc2-8-g594f506 (Jun 10 2015
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