Re: [U-Boot] [PATCH 4/7] fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC

Dear Kyle Moffett, In message <1298311199-18775-5-git-send-email-kyle.d.moff...@boeing.com> you wrote: > The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit > integer divide operations to convert between nanoseconds and DDR clock > cycles given arbitrary DDR clock frequencies.

[U-Boot] [PATCH 4/7] fsl_ddr: Don't use full 64-bit divides on 32-bit PowerPC

The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit integer divide operations to convert between nanoseconds and DDR clock cycles given arbitrary DDR clock frequencies. Since all of the inputs to this are 32-bit (nanoseconds, clock cycles, and DDR frequencies), we can easily re