On Feb 8, 2011, at 2:51 PM, Haiying Wang wrote:
> P1021 has some QE pins which need to be set in pmuxcr register before using QE
> functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth
> mode.
> QE9 and QE12 are set for MII management. QE12 needs to be released after MII
> a
P1021 has some QE pins which need to be set in pmuxcr register before using QE
functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode.
QE9 and QE12 are set for MII management. QE12 needs to be released after MII
access because QE12 pin is muxed with LBCTL signal.
Signed-of
2 matches
Mail list logo
