Re: [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

2013-11-26 Thread Andre Przywara
On 11/21/2013 09:59 AM, Marc Zyngier wrote: A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Makes sense ;-) and works on the VExpress TC2. Albert, Tom, please apply for v2014.01. Acked-by: Andre Przywara Signed-off-by: Marc Zyngie

Re: [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

2013-11-22 Thread Christoffer Dall
On Fri, Nov 22, 2013 at 10:56:05AM +, Marc Zyngier wrote: > On 22/11/13 01:51, Christoffer Dall wrote: > > On 21 November 2013 00:59, Marc Zyngier wrote: > >> A CP15 instruction execution can be reordered, requiring an > >> isb to be sure it is executed in program order. > >> > >> Signed-off-b

Re: [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

2013-11-22 Thread Marc Zyngier
On 22/11/13 01:51, Christoffer Dall wrote: > On 21 November 2013 00:59, Marc Zyngier wrote: >> A CP15 instruction execution can be reordered, requiring an >> isb to be sure it is executed in program order. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm/cpu/armv7/nonsec_virt.S | 1 + >> 1 f

Re: [U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

2013-11-21 Thread Christoffer Dall
On 21 November 2013 00:59, Marc Zyngier wrote: > A CP15 instruction execution can be reordered, requiring an > isb to be sure it is executed in program order. > > Signed-off-by: Marc Zyngier > --- > arch/arm/cpu/armv7/nonsec_virt.S | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/ar

[U-Boot] [PATCH 3/9] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1

2013-11-21 Thread Marc Zyngier
A CP15 instruction execution can be reordered, requiring an isb to be sure it is executed in program order. Signed-off-by: Marc Zyngier --- arch/arm/cpu/armv7/nonsec_virt.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S ind