> -Original Message-
> From: Horia Geanta
> Sent: Wednesday, July 31, 2019 1:24 AM
> To: Laurentiu Tudor ; u-boot@lists.denx.de;
> Prabhakar Kushwaha
> Subject: Re: [PATCH 3/5] armv8: fsl-layerscape: make icid setup endianness
> aware
>
> On 7/30/2019 5:30 PM, laurentiu.tu...@nxp.com wro
On 7/30/2019 5:30 PM, laurentiu.tu...@nxp.com wrote:
> From: Laurentiu Tudor
>
> The current implementation assumes that the registers holding the ICIDs
> are universally big endian. That's no longer the case on newer
> platforms so update the code to take into account the endianness of
> each re
From: Laurentiu Tudor
The current implementation assumes that the registers holding the ICIDs
are universally big endian. That's no longer the case on newer
platforms so update the code to take into account the endianness of
each register.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/
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