On 12/07/2015 04:58 PM, Mingkai Hu wrote:
> Consecutive write transactions from core to PCI express outbound
> path hangs after 25 to 30 transactions depending on core freq.
> This erratum enable the mbist clock through COP register setting.
>
> Signed-off-by: Mingkai Hu
> ---
Applied to u-boo
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 16
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