Hi Chis,
On 15.02.19 12:57, Chris Packham wrote:
On Fri, 15 Feb 2019, 11:06 PM Stefan Roese mailto:s...@denx.de>
wrote:
Hi Chris,
On 15.02.19 10:41, Chris Packham wrote:
> Marvell's switch chips with integrated CPUs (collectively referred to as
> MSYS) share common ancestr
On Fri, 15 Feb 2019, 11:06 PM Stefan Roese Hi Chris,
>
> On 15.02.19 10:41, Chris Packham wrote:
> > Marvell's switch chips with integrated CPUs (collectively referred to as
> > MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
> > (e.g. xor) are located at different addresse
Hi Chris,
On 15.02.19 10:41, Chris Packham wrote:
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS
Marvell's switch chips with integrated CPUs (collectively referred to as
MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks
(e.g. xor) are located at different addresses and DFX server exists as a
separate target on the MBUS (on Armada-38x it's just part of the core
complex reg
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