Hi Cédric,
On 25/01/19 11:30 PM, Boris Brezillon wrote:
> +Vignesh
>
[...]
>> The first is about performing direct accesses on the AHB window on which
>> the flash contents is mapped.
>
> We have introduced the dirmap API/interface exactly for this purpose,
> and the SPI NOR layer will use it i
+Vignesh
Hi Cédric,
On Fri, 25 Jan 2019 18:28:02 +0100
Cédric Le Goater wrote:
> Hello
>
> On 10/10/18 2:02 PM, Cédric Le Goater wrote:
> > Hello Boris,
> >
> > On 10/10/18 9:32 AM, Boris Brezillon wrote:
> >> Hi Cédric,
> >>
> >> On Wed, 10 Oct 2018 11:46:56 +0530
> >> Jagan Teki wrote:
>
Hello
On 10/10/18 2:02 PM, Cédric Le Goater wrote:
> Hello Boris,
>
> On 10/10/18 9:32 AM, Boris Brezillon wrote:
>> Hi Cédric,
>>
>> On Wed, 10 Oct 2018 11:46:56 +0530
>> Jagan Teki wrote:
>>
>>> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
On 10/4/18 5:57 PM, Jagan Teki w
Hello Boris,
On 10/10/18 9:32 AM, Boris Brezillon wrote:
> Hi Cédric,
>
> On Wed, 10 Oct 2018 11:46:56 +0530
> Jagan Teki wrote:
>
>> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
>>>
>>> On 10/4/18 5:57 PM, Jagan Teki wrote:
On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater w
Hi Cédric,
On Wed, 10 Oct 2018 11:46:56 +0530
Jagan Teki wrote:
> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
> >
> > On 10/4/18 5:57 PM, Jagan Teki wrote:
> > > On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater wrote:
> > >>
> > >> Hello Simon,
> > >>
> > >>
> > >> The Aspeed A
On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater wrote:
>
> On 10/4/18 5:57 PM, Jagan Teki wrote:
> > On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater wrote:
> >>
> >> Hello Simon,
> >>
> >>
> >> The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash
> >> memory,
> >> and the Aspee
Hello Simon,
[...]
+/* CEx Control Register */
+#define CE_CTRL_IO_MODE_MASK GENMASK(30, 28)
+#define CE_CTRL_IO_DUAL_DATA BIT(29)
+#define CE_CTRL_IO_DUAL_ADDR_DATA (BIT(29) | BIT(28))
+#define CE_CTRL_CMD_SHIFT 16
+#define CE_C
On 10/4/18 5:57 PM, Jagan Teki wrote:
> On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater wrote:
>>
>> Hello Simon,
>>
>>
>> The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash memory,
>> and the Aspeed AST2500 SPI Flash Controllers only SPI. If there is some
>> misunderstanding on
On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater wrote:
>
> Hello Simon,
>
>
> The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash memory,
> and the Aspeed AST2500 SPI Flash Controllers only SPI. If there is some
> misunderstanding on this driver, it might come from the fact it is
Hi Cedric,
On 28 September 2018 at 04:42, Cédric Le Goater wrote:
> Hello Simon,
>
>
> The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash memory,
> and the Aspeed AST2500 SPI Flash Controllers only SPI. If there is some
> misunderstanding on this driver, it might come from the f
Hello Simon,
The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash memory,
and the Aspeed AST2500 SPI Flash Controllers only SPI. If there is some
misunderstanding on this driver, it might come from the fact it is closer
to a SPI-NOR driver like we have in Linux, than a generic S
Hi Cedric,
On 10 September 2018 at 07:16, Cédric Le Goater wrote:
> The Aspeed AST2500 SoC comes with three static memory controllers, all
> with a similar interface :
>
> * Firmware SPI Memory Controller (FMC)
>. BMC firmware
>. 3 chip select pins (CE0 ~ CE2)
>. supports SPI type fl
On 09/12/2018 12:38 AM, Joel Stanley wrote:
> On Mon, 10 Sep 2018 at 23:48, Cédric Le Goater wrote:
>>
>> The Aspeed AST2500 SoC comes with three static memory controllers, all
>> with a similar interface :
>>
>> * Firmware SPI Memory Controller (FMC)
>>. BMC firmware
>>. 3 chip select pi
On Mon, 10 Sep 2018 at 23:48, Cédric Le Goater wrote:
>
> The Aspeed AST2500 SoC comes with three static memory controllers, all
> with a similar interface :
>
> * Firmware SPI Memory Controller (FMC)
>. BMC firmware
>. 3 chip select pins (CE0 ~ CE2)
>. supports SPI type flash memory
The Aspeed AST2500 SoC comes with three static memory controllers, all
with a similar interface :
* Firmware SPI Memory Controller (FMC)
. BMC firmware
. 3 chip select pins (CE0 ~ CE2)
. supports SPI type flash memory (CE0 ~ CE1)
. CE2 can be of NOR type flash but this is not supporte
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