Re: [U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53

2012-10-17 Thread Stefano Babic
Am 15/10/2012 17:37, schrieb Fabio Estevam: > Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. > > Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz > instead. > > Without doing so, it is not possible to use a 2.6.35 FSL kernel and display

[U-Boot] [PATCH 2/3] mx5: lowlevel_init.S: Fix PLL settings for mx53

2012-10-15 Thread Fabio Estevam
Currently PLL2 is not explicitely configured for mx53 and it runs at 333MHz. Since PLL2 is the parent clock for DDR2, IPU, VPU, we should set it at 400MHz instead. Without doing so, it is not possible to use a 2.6.35 FSL kernel and display HDMI at 1080p because the IPU clock cannot reach the req