> On 04/01/2016 12:09 AM, Sumit Garg wrote:
> > For mpc85xx SoCs, the core begins execution from address 0xFFFC.
> > In non-secure boot scenario from NAND, this address will map to CPC
> > configured as SRAM. But in case of secure boot, this default address
> > always maps to IBR (Internal Boo
On 04/01/2016 12:09 AM, Sumit Garg wrote:
> For mpc85xx SoCs, the core begins execution from address 0xFFFC.
> In non-secure boot scenario from NAND, this address will map to CPC
> configured as SRAM. But in case of secure boot, this default address
> always maps to IBR (Internal Boot ROM).
> T
For mpc85xx SoCs, the core begins execution from address 0xFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) mus
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