On Mon, Oct 19, 2009 at 7:55 AM, Dirk Behme wrote:
> Steve Sakoman wrote:
>>
>> On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon wrote:
>>>
>>> Defaults are for Infineon DDR timings.
>>> Since none of the supported boards currently do
>>> XIP boot, these seem to be faulty. fix the values
>>> as per
Steve Sakoman wrote:
> On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon wrote:
>> Defaults are for Infineon DDR timings.
>> Since none of the supported boards currently do
>> XIP boot, these seem to be faulty. fix the values
>> as per the calculations(ACTIMA,B), conf
>> the sdrc power with pwdnen an
On Tue, Oct 6, 2009 at 7:17 PM, Nishanth Menon wrote:
> Defaults are for Infineon DDR timings.
> Since none of the supported boards currently do
> XIP boot, these seem to be faulty. fix the values
> as per the calculations(ACTIMA,B), conf
> the sdrc power with pwdnen and wakeupproc bits
>
> Signed
>
> Defaults are for Infineon DDR timings.
> Since none of the supported boards currently do
> XIP boot, these seem to be faulty. fix the values
> as per the calculations(ACTIMA,B), conf
> the sdrc power with pwdnen and wakeupproc bits
>
> Signed-off-by: Nishanth Menon
> Cc: David B
> Cc: Vikra
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon
Cc: David B
Cc: Vikram Pandita
Cc: Richar
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