Hi Ajay,
On Tue, Dec 11, 2012 at 3:01 AM, Ajay Kumar wrote:
> With VPLL as source clock to FIMD,
> Exynos DP Initializaton was failing sometimes with unstable clock.
> Changing FIMD source to resolves this issue.
>
> Signed-off-by: Ajay Kumar
Acked-by: Simon Glass
At some point it would be ni
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to resolves this issue.
Signed-off-by: Ajay Kumar
---
arch/arm/cpu/armv7/exynos/clock.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cp
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