On 03/19/2015 09:30 AM, York Sun wrote:
> Add/update registers for DDR4, including DQ mappings. Allow raw timing
> method used for all controllers. Update mode_9 register to 0x500 for
> improved stability. Check DDR controller version number individually
> in case a SoC has multiple DDR controlle
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turn
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