On 01/21/2015 01:29 AM, Minghuan Lian wrote:
> LS1021A's PCIe1 region begins 0x40_; PCIe2 begins
> 0x48_. In order to access PCIe device, we must create
> TLB to map the 40bit physical address to 32bit virtual address.
> This patch will enable MMU after DDR is available and create
LS1021A's PCIe1 region begins 0x40_; PCIe2 begins
0x48_. In order to access PCIe device, we must create
TLB to map the 40bit physical address to 32bit virtual address.
This patch will enable MMU after DDR is available and creates MMU
table in DRAM to map all 4G space; then, re-use t
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