Dear Wolfgang,
Thanks for the feedback.
> ...
> > +int misc_init_r(void)
> > +{
> ...
> > + /* reset all SGMII interfaces */
> > + mfsdr(SDR0_SRST1, reg);
> > + reg |= (SDR0_SRST1_SGMII0 | SDR0_SRST1_SGMII1 | SDR0_SRST1_SGMII2);
> > + mtsdr(SDR0_SRST1, reg);
> > + mtsdr(SDR0_ETH_STS,
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board
> is a dual processor board with each processor providing independent resources
> for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has
The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is
a dual processor board with each processor providing independent resources for
Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own
512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and tempe
3 matches
Mail list logo