Re: [U-Boot] [PATCH 1/3] net: designware: socfpga: adapt to Gen5

On 1/10/19 9:42 PM, Simon Goldschmidt wrote: > > > Am Do., 10. Jan. 2019, 21:38 hat Marek Vasut > geschrieben: > > On 1/10/19 8:54 PM, Simon Goldschmidt wrote: > > Hi Marek, > > > > Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt: > >> This driver was

Re: [U-Boot] [PATCH 1/3] net: designware: socfpga: adapt to Gen5

Am Do., 10. Jan. 2019, 21:38 hat Marek Vasut geschrieben: > On 1/10/19 8:54 PM, Simon Goldschmidt wrote: > > Hi Marek, > > > > Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt: > >> This driver was written for Arria10, but it applies to Gen5, too. > >> > >> The main difference is that Gen5 has 2

Re: [U-Boot] [PATCH 1/3] net: designware: socfpga: adapt to Gen5

On 1/10/19 8:54 PM, Simon Goldschmidt wrote: > Hi Marek, > > Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt: >> This driver was written for Arria10, but it applies to Gen5, too. >> >> The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the >> syscon bits are encoded in the same regis

Re: [U-Boot] [PATCH 1/3] net: designware: socfpga: adapt to Gen5

Hi Marek, Am 10.01.2019 um 20:49 schrieb Simon Goldschmidt: This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read

[U-Boot] [PATCH 1/3] net: designware: socfpga: adapt to Gen5

This driver was written for Arria10, but it applies to Gen5, too. The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the syscon bits are encoded in the same register, thus an offset is needed. This offset is already read from the devicetree, but for Arria10 it is always 0, which is p