Re: [U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

nx.de > Subject: Re: [U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR > erratum A008514 > > >Hi Yuan > > On 14/08/15 02:54 AM, Yuan Yao wrote: > > Affects: DDR > > Description: Memory controller performance is not optimal with default > > int

Re: [U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

On 08/13/2015 11:54 PM, Yuan Yao wrote: > Affects: DDR > Description: Memory controller performance is not optimal with default > internal target queue register values. > Impact: Memory controller performance is not optimal. > Workaround: Write a value of 63b2_0002h to address: 157_020Ch. > > Si

Re: [U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Hi Yuan On 14/08/15 02:54 AM, Yuan Yao wrote: Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch. Signed

[U-Boot] [PATCH 1/3] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

Affects: DDR Description: Memory controller performance is not optimal with default internal target queue register values. Impact: Memory controller performance is not optimal. Workaround: Write a value of 63b2_0002h to address: 157_020Ch. Signed-off-by: Yuan Yao --- arch/arm/include/asm/arch-ls