Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

2013-08-14 Thread Tom Warren
ephen Warren > Subject: Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC > specific > > On 07/18/2013 01:13 PM, Thierry Reding wrote: > > From: Thierry Reding > > > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > > i

Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

2013-08-14 Thread Stephen Warren
On 07/18/2013 01:13 PM, Thierry Reding wrote: > From: Thierry Reding > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > therefore uses a cache line size of 64 bytes. Move the cache line size > setting

Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

2013-07-18 Thread Stephen Warren
On 07/18/2013 08:38 PM, Thierry Reding wrote: > On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote: >> On 07/18/2013 01:13 PM, Thierry Reding wrote: >>> From: Thierry Reding >>> >>> Currently all Tegra SoCs are assumed to have 32 byte cache >>> lines. This isn't true for Tegra114, how

Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

2013-07-18 Thread Thierry Reding
On Thu, Jul 18, 2013 at 03:19:18PM -0600, Stephen Warren wrote: > On 07/18/2013 01:13 PM, Thierry Reding wrote: > > From: Thierry Reding > > > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > > there

Re: [U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

2013-07-18 Thread Stephen Warren
On 07/18/2013 01:13 PM, Thierry Reding wrote: > From: Thierry Reding > > Currently all Tegra SoCs are assumed to have 32 byte cache lines. This > isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and > therefore uses a cache line size of 64 bytes. Move the cache line size > setting

[U-Boot] [PATCH 1/2] ARM: tegra: Make cache line size SoC specific

2013-07-18 Thread Thierry Reding
From: Thierry Reding Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: