Re: [U-Boot] [PATCH 1/2] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling

2013-11-07 Thread Sricharan R
Hi Tom, On Thursday 07 November 2013 08:33 PM, Tom Rini wrote: > On Thu, Nov 07, 2013 at 08:17:39PM +0530, Sricharan R wrote: > >> Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using >> software leveling. This was done since hardware leveling was not >> working. Now that the right s

Re: [U-Boot] [PATCH 1/2] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling

2013-11-07 Thread Tom Rini
On Thu, Nov 07, 2013 at 08:17:39PM +0530, Sricharan R wrote: > Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using > software leveling. This was done since hardware leveling was not > working. Now that the right sequence to do hw leveling is identified, > use it. This is required fo

[U-Boot] [PATCH 1/2] ARM: DRA: EMIF: Change DDR3 settings to use hw leveling

2013-11-07 Thread Sricharan R
Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using software leveling. This was done since hardware leveling was not working. Now that the right sequence to do hw leveling is identified, use it. This is required for EMIF clockdomain to idle and come back during lowpower usecases. Si