Hi,
On Sat, 6 Oct 2012 22:16:04 +0800
Liu Ying wrote:
> From: Liu Ying
>
> This patch checks self-clear sw_ipu_rst bit in
> SCR register of SRC controller to be cleared
> after setting it to high to reset IPUv3. This
> makes sure that IPUv3 finishes sofware reset.
> A timeout mechanism is added
From: Liu Ying
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleare
Hi Liu Ying,
On 10/06/2012 07:16 AM, Liu Ying wrote:
From: Liu Ying
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop pollin
On Sat, Oct 6, 2012 at 9:59 AM, Fabio Estevam wrote:
> Hi Liu Ying,
>
> On Sat, Oct 6, 2012 at 7:32 AM, Liu Ying wrote:
>
>> @@ -397,6 +397,9 @@ void ipu_reset(void)
>> value = __raw_readl(reg);
>> value = value | SW_IPU_RST;
>> __raw_writel(value, reg);
>> +
>> + wh
Hi Liu Ying,
On Sat, Oct 6, 2012 at 7:32 AM, Liu Ying wrote:
> @@ -397,6 +397,9 @@ void ipu_reset(void)
> value = __raw_readl(reg);
> value = value | SW_IPU_RST;
> __raw_writel(value, reg);
> +
> + while (__raw_readl(reg) & SW_IPU_RST)
> + ;
Ok, but i
From: Liu Ying
This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
Signed-off-by: Liu Ying
---
drivers/video/ipu_common.c |3 +++
1 files changed, 3 insertion
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